OZ1KLK

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(last edit: 24. september 2012)

Procedure

Used to group together executable, sequential statements. A procedure has a name and a set of parameters. The values of the parameters are passed in or out when the procedure is called. When defined in a package, the procedure must be split into a declaration and a body.

Syntax

 {declaration}
 procedure ProcedureName [(ParameterDeclaration; ...)];

 {body}
 procedure ProcedureName [(ParameterDeclaration; ...)] is
   Declarations...
 begin
   SequentialStatements...
 end [procedure] [ProcedureName];

 ParameterDeclaration = {either}
 constant ConstantName,...: [in]  DataType [:=Expression]
 signal   SignalName,  ...: [Mode]DataType [:=Expression]
 variable VariableName,...: [Mode]DataType [:=Expression]
 file FileName, ... : DataType

 Mode = {either} in out inout

Where

See Declaration A Procedure Body is not allowed in a Package Declaration.

Rules

Mode defaults to in. Parameters of mode in default to constant. Parameters of mode out or inout default to variable. The Expression gives the default value of the parameter. A parameter with no default value must be given a value in the procedure call. A procedure containing a signal assignment (other than to a parameter of the procedure) must be declared inside a process.

Things to remember

Variables defined inside a procedure are initialized each time the procedure is called. A procedure containing assignments to signals (other than parameters) must be defined in a process. The procedure declaration and body must conform, i.e. the parameters must be identical between the two. The procedure declaration ends with a ";", whereas the procedure body has is at the corresponding point.

Synthesis

Procedures are synthesizable, provided that they do not detect clock edges or contain wait statements, i.e. they must not infer registers or states.

Tips

Parameters may be unconstrained arrays; you can use array attributes (e.g. 'RANGE) to find their bounds.

Example

  procedure ASSIGN (signal Clock: in Std_logic;
                    Values: Std_logic_vector;
                    signal X, Y: out Std_logic;
                    variable V, W: out Std_logic;
                    PAUSE: TIME := 10 NS) is
  begin
    if Clock'EVENT and Clock = '1' then
      X <= Values(0);
      Y <= Values(1);
      V := Values(2);
      W := Values(3);
      wait for PAUSE;
    end if;
  end ASSIGN;
  ...
  -- Procedure call...
  ASSIGN (Clock, "0101", S1, S2, V1, V2);